Heretofore, there has been an IC analysis system of the type that scans and irradiates an IC chip a charged particle beam, measures the quantity of secondary electrons emitted from the IC chip at each irradiated point in terms of an electric signal, and processes the electrical signal to display the potential distribution in the IC chip as a potential contrast image that is available for analyzing a fault in the IC chip.
This assignee disclosed the related technologies in the Japanese Patent Application No. 5-190440 entitled "Electron Beam Tester and IC Analysis System Incorporating Thereof", and in the Japanese Patent Application No. 5-257625 entitled "Method for Locating Faulty Part of IC". Moreover, this assignee disclosed the related technology in the Japanese Patent Application No. 6-101938 entitled "Method for Locating Faulty Part of IC Utilizing Ion Beam Tester and IC Analysis System Incorporating Ion Beam Tester".
The present invention is applicable to all kinds of charged particle beam apparatus including an electron beam tester and an ion beam tester. In the present invention, the term "charged particle beam apparatus" includes both an ion beam tester and an electron beam tester. Moreover, in the context of this invention, the term "charged particle beam" includes both an ion beam and an electron beam.
FIG. 18 shows a general construction of the conventional type IC analysis system. Reference numeral 100 denotes the general view of an IC analysis system, which is made up of a test pattern generator 200 and a charged particle beam apparatus 300. The test pattern generator 200 provides a test pattern signal to an IC under test (which will hereinafter be referred to also as a device under test DUT) placed in the charged particle beam apparatus 300.
The conventional test pattern generator 200 includes; a start switch 201 for starting the generation of the test pattern; a stop switch 202 for stopping the generation of the test pattern at an arbitrary point of time; stop pattern setting means 203 for stopping the updating of the test pattern when a specified test pattern is generated; pattern holding means 204 for stopping the updating of the test pattern by detecting the test pattern set to the stop pattern setting means 203; and stop signal generating means 205 for generating a signal indicating the stop of the updating of the test pattern. Because of this arrangement, the test pattern generator 200 can control a start and stop of the test pattern signal and a stop of the updating of a specific test pattern.
The charged particle beam apparatus 300 is made up of; a column part 301 which irradiates a device under test DUT a charged particle beam; a chamber 302 which is provided just under the column part 301 to hold the device under test DUT in a vacuum; a stage 303 which is provided in the chamber 302 to shift the position of the device under test DUT in the X-Y direction; a sensor 304 for measuring the quantity of secondary electrons from the device under test DUT as an electrical signal; an image data acquiring apparatus 305 which fetches therein, as image data, the electrical signal detected by the sensor 304; a monitor 306 which displays, as a potential contrast image, the image data processed by the image data acquiring apparatus 305; and a column controller 307 which controls the emission of the charged particle beam, the quantity of its emission (an electric current value), an acceleration voltage, a scanning speed, a scanning area, and etc.
When detecting that the test pattern generator 200 has generated a test pattern set in the stop pattern setting means 203, the pattern holding means 204 suspends its test pattern updating operation and maintains the test pattern output at that time. AT the same time, the stop signal generating means 205 supplies the image data acquiring apparatus 305 and the column controller 307 a stop signal representing that the test pattern updating operation has stopped. Upon receiving the stop signal, the column controller 307 effects control to emit the charged particle beam and image data acquiring apparatus 305 begins to fetch therein image data.
The method to specify an IC fault is accomplished by setting a test pattern that causes failure in the device under test DUT in the stop pattern setting means 203. It has already been checked in an IC tester that the test pattern causes failure in the DUT (but not a specific location in the DUT). On detecting that the test pattern generator 200 has generated the test pattern that was set in the stop pattern setting means 203 and that also causes failure, the test pattern generator 200 suspends the test pattern updating operation and maintains the test pattern set in the stop pattern setting means 203. Upon receiving the stop signal, the column controller 307 effects control to emit the charged particle beam and image data acquiring apparatus 305 begins to fetch therein image data. The above procedures up to the fetching the image data in the image data acquiring apparatus 305 are performed for both the normal state and the faulty state of the device under test DUT. The image data acquiring apparatus 305 compares the image data, and then the difference between both image data is identified as a fault.
Conventionally, the time for suspension of the test pattern is set slightly longer than the time for writing the image data in the image data acquiring apparatus 305. As a consequence, a change in the conditions for writing the image data in the image data acquiring apparatus requires the change in the test pattern suspension time as well. Therefore, the prior art IC analysis system has a disadvantage in its operability.
That is, a charged particle beam acceleration voltage, a scanning speed, a scanning area, a scanning time, etc. must be set for capturing image data, and if these conditions are changed or modified, the time for acquiring image data will change. Consequently, when the conditions for capturing image data are changed, the test pattern suspension time also needs to be changed accordingly. This involves operating both of the test pattern generator 200 and the charged particle beam apparatus 300, and hence is troublesome.
On the other hand, the conditions for writing the image data in the image data acquiring apparatus 305 needs to be changed in accordance with the purpose of each test. In particular, in the case where the device under test DUT is an IC chip which is covered all over with an insulating film as a protective layer, it is necessary to observe or measure potentials corresponding to those of wiring conductors underlying the insulating film. It is difficult, however, to detect, as a potential contrast image, the potential distributions of the wiring conductors of the IC chip which is covered with the insulating film.
That is, when the surface of the insulating film is irradiated with a charged particle beam, the potential distribution ultimately disappears owing to the storage of charges on the insulating film in proportion to the charged particle beam emanating time, and as a result, it is impossible to detect a desired potential contrast image. FIG. 19 shows such a situation where the potential distribution of the IC chip surface disappears.
In FIG. 19A, the potential contrast image is illustrated wherein conductors L1, L2, L3 and L4 that are underlying the insulating film and that have been supplied with L-logic, H-logic, L-logic and H-logic potentials, respectively. As shown, the application of the L-logic potential (a voltage close to zero volt or negative potential) provides a white potential contrast image (which means that the quantity of secondary electrons reaching a sensor 304 is large). The application of the H-logic potential (a positive voltage exceeding zero volt) provides a black potential contrast image (which means that the quantity of secondary electrons reaching the sensor 304 is small). In this instance, an insulating substrate PB has an intermediate potential between the L-logic and H-logic potentials and is displayed in gray.
FIGS. 19B and 19C show potential contrast images appearing (in 0.1 to 0.3 seconds) after the scanning irradiation with the charged particle beam. As will be seen from these drawings, when the charged particle beam is applied, the potential contrast rapidly lowers as in FIG. 19B and finally disappears as in FIG. 19C. Thus, necessary image data can be obtained only when the potential contrast is in such a state as shown in FIG. 19A. In other words, it is difficult to obtain a clear image by only a single fetch of image data because the potential contrast can not be held for a long time.
Owing to the presence of such a potential contrast reduction phenomenon, the conditions for acquiring the image data, i.e., the area to be scanned with the charged particle beam, the current value of the charged particle beam, etc., must be changed frequently. However, each time the conditions for acquiring the image data are changed, the time interval for which the updating of the test pattern is suspended must also be reset, which is time consuming and impairs the operability of the system.
In the IC analysis system having the charged particle beam apparatus, the potential contrast image is obtained through the steps of scanning and irradiating one area of the device under test DUT with a charged particle beam, applying thereto a desired test pattern and acquiring the quantity of secondary electrons as image data. In the case of an IC chip of which the surface is covered with an insulating film, however, as noted above, there is the phenomenon that the potential distribution formed on the insulating film disappears in proportion to the quantity of the charged particle beam irradiation as described previously. On this account, only image data acquired under one scanning irradiation with the charged particle beam becomes effective. Moreover, such small quantity of the image data as acquired under one scanning irradiation with the charged particle beam, stored into an image memory, etc. and read out repeatedly, causes a defect that the potential contrast image can not be finely and clearly displayed in a monitor 306.
One possible solution to this problem is to update test patterns one after another and continue the scanning irradiation with the charged particle beam until the specific test pattern n is generated. In this method, since the IC chip is irradiated with the charged particle beam while the test patterns are updated at high speed, the potential of the insulating film covering the surface of the IC chip becomes a mean value of potential variations of the wiring conductors, that is, an intermediate value between the H-logic and the L-logic. When the pattern updating operation stops upon generation of the specified test pattern n, the potential distribution dependent on the test pattern can be captured as a potential contrast image.
After acquiring the image data, by resuming the pattern updating operation and further continuing the scanning irradiation with the charged particle beam, the potential of the insulating film takes again the intermediate value between the H-logic and the L-logic. By repeating this process, the potential contrast image corresponding to the desired test pattern being supplied can be obtained. This increases the quantity of image data, and the picture quality of the voltage contrast image can be enhanced.
However, this method still has disadvantages as mentioned below. That is, according to the potential immediately prior to the suspension of the pattern updating operation upon generation of a desired test pattern, some wiring conductors may be displayed as potential contrast images but other wiring conductors may not, which is not desirable for the fault analysis.